As semiconductor memory technology progresses there is an increasing need for on-chip testing, examination and evaluation. It has conventionally been the practice to functionally test a memory circuit by conducting various combinations of the usual read and write operations. However, this is becoming increasingly difficult. As the capacity of memory circuits becomes larger, the time required to test the circuits increases. For certain types of tests, such as for pattern sensitivities, the number of testing steps can be proportional to the square of the number of memory elements. Thus, comprehensive testing for large random access memories can become excessively time consuming.
A further feature which must be considered in testing is that of redundancy. The use of redundant circuit elements to replace defective circuit elements has been adopted to increase the yield of usable devices. Certain users of semiconductor memories are especially interested in pattern sensitivities in the testing of these parts. With a fixed physical layout, without redundancy, a fixed testing procedure can be carried out for each type of part. However, with the advent of redundancy the user has not been able to know for certain the physical layout of the operational elements within the memory. Without this knowledge the user may be reluctant to accept a part which may have had a redundant element substituted into the primary memory array.
The functional operation of the circuit with redundancy is essentially the same as that of one without redundancy. Therefore, the user, by conventional functional testing, cannot determine whether redundant elements have been implemented into the circuit.
On-chip testing or examination has been proposed to reduce the testing requirements for memory circuits. However, there are serious limitations in attempting to do this. The conventional packaging for dynamic random access memories is a 16-pin package for which standard definitions have been made for each of the pins. Therefore, there are virtually no pins available for receiving additional commands to carry out on-chip testing. Further, the use of excessive voltage states on certain pins to command special functions is a hazardous practice since it is possible to damage the circuit in doing so.
The data sheets for semiconductor memories have limiting specifications that define the timing for each of the command signals applied to the memory circuit. The user of the circuit must comply with these specifications to insure proper operation of the circuit. In addition, the designer of the circuit must insure that the circuit responds only to the design specifications such that the user can be confident that the part will function in the manner he desires.
From the above it can be seen that there is a substantial need to provide on-chip functional test and examination but that there are severe restrictions placed upon the transmission of command signals to the memory circuit. Thus, there exists a need for a method and apparatus for providing additional functional commands to a semiconductor memory circuit without adding to the pin count for the part, avoiding the use of excessive voltage states and without altering the well accepted data sheet specifications.